1. Field of the Invention
The present invention relates to an address-while-display driving method for a plasma display panel, and more particularly, to an address-while-display driving method for a surface discharge type triode plasma display panel.
2. Description of the Related Art
FIG. 1 shows the structure of a conventional surface discharge type triode plasma display panel (PDP) 1. FIG. 2 shows an example of a display cell of the PDP 1 shown in FIG. 1. Referring to FIGS. 1 and 2, address electrode lines A1, A2, . . . , Am-1, Am; front and rear dielectric layers 11 and 15; Y-electrode lines Y1, . . . , Yn; X-electrode lines X1, . . . , Xn; phosphor layers 16; partition walls 17; and a magnesium oxide (MgO) layer 12 as a protective layer are provided between front and rear glass substrates 10 and 13 of a general surface discharge PDP 1.
The address electrode lines A1 through Am are formed on the front surface of the rear glass substrate 13 in a predetermined pattern. A rear dielectric layer 15 is formed on the entire surface of the rear glass substrate 13 having the address electrode lines A1 through Am. The partition walls 17 are formed on the front surface of the rear dielectric layer 15 to be parallel to the address electrode lines A1 through Am. These partition walls 17 define the discharge areas of respective display cells and serve to prevent cross talk between display cells. The phosphor layers 16 are deposited between partition walls 17.
The X-electrode lines X1 through Xn and the Y-electrode lines Y1 through Yn are formed on the rear surface of the front glass substrate 10 in a predetermined pattern to be orthogonal to the address electrode lines A1 through Am. The respective intersections define display cells. Each of the X-electrode lines X1 through Xn is composed of a transparent electrode line Xna (FIG. 2) formed of a transparent conductive material, e.g., indium tin oxide (ITO), and a metal electrode line Xnb (FIG. 2) for increasing conductivity. Each of the Y-electrode lines Y1 through Yn is composed of a transparent electrode line Yna (FIG. 2) formed of a transparent conductive material, e.g., ITO, and a metal electrode line Ynb (FIG. 2) for increasing conductivity. A front dielectric layer 11 is deposited on the entire rear surface of the front glass substrate 10 having the rear surfaces of the X-electrode lines X1 through Xn and the Y-electrode lines Y1 through Yn. The protective layer 12, e.g., a MgO layer, for protecting the PDP 1 against a strong electrical field is deposited on the entire surface of the front dielectric layer 1. A gas for forming plasma is hermetically sealed in a discharge space 14.
FIG. 3 shows a typical address-display separation driving method with respect to Y-electrode lines of the PDP 1 shown in FIG. 1. Referring to FIG. 3, to realize time-division gray scale display, a unit frame is divided into 8 subfields SF1 through SF8. In addition, the individual subfields SF1 through SF8 are composed of address periods A1 through A8, respectively, and display periods S1 through S8, respectively.
During each of the address periods A1 through A8, display data signals are applied to the address electrode lines A1 through Am of FIG. 1, and simultaneously, a scan pulse is sequentially applied to the Y-electrode lines Y1 through Yn. If a high-level display data signal is applied to some of the address electrode lines A1 through Am while the scan pulse is applied, wall charges are induced from address discharge only in relevant display cells.
During each of the display periods S1 through S8, a display discharge pulse is alternately applied to the Y-electrode lines Y1 through Yn, and the X-electrode lines X1 through Xn, thereby provoking display discharge in display cells in which wall charges are induced during each of the address periods A1 through A8. Accordingly, the brightness of a PDP is proportional to a total length of the display periods S1 through S8 in a unit frame. The total length of the display periods S1 through S8 in a unit frame is 255T (T is a unit time). Accordingly, including the case where the display is not performed in a unit frame, 256 gray scales can be displayed. This is explained below.
Here, the display period S1 of the first subfield SF1 is set to a time 1T corresponding to 20. The display period S2 of the second subfield SF2 is set to a time 2T corresponding to 21. The display period S3 of the third subfield SF3 is set to a time 4T corresponding to 22. The display period S4 of the fourth subfield SF4 is set to a time 8T corresponding to 23. The display period S5 of the fifth subfield SF5 is set to a time 16T corresponding to 24. The display period S6 of the sixth subfield SF6 is set to a time 32T corresponding to 25. The display period S7 of the seventh subfield SF7 is set to a time 64T corresponding to 26. The display period S8 of the eighth subfield SF8 is set to a time 128T corresponding to 27.
Accordingly, if a subfield to be displayed is appropriately selected from among 8 subfields, a total of 256 gray scales can be displayed including a gray level of zero at which display is not performed in any subfield.
According to the above-described address-display separation display method, the time domains of the respective subfields SF1 through SF8 are separated, so the time domains of respective address periods of the subfields SF1 through SF8 are separated, and the time domains of respective display periods of the subfields SF1 through SF8 are separated. Accordingly, during a given address period, an XY-electrode line pair is kept waiting after being addressed until all of the other XY-electrode line pairs are addressed. Consequently, in each subfield, an address period increases, and a display period decreases. As a result, the brightness of light emitted from a PDP decreases. An existing method proposed for overcoming this problem is an address-while-display driving method as shown in FIG. 4.
FIG. 4 shows a typical address-while-display driving method with respect to the Y-electrode lines of the PDP 1 shown in FIG. 1. Referring to FIG. 4, to realize time-division gray scale display, a unit frame is divided into 8 subfields SF1 through SF8. Here, the subfields SF1 through SF8 overlap with respect to the Y-electrode lines Y1 through Yn and constitute a unit frame. Since all of the subfields SF1 through SF8 exist at any time point, address time slots are set among display discharge pulses in order to perform each address step.
In each of the subfields SF1 through SF8, a reset step, address step, and display discharge step are performed. A time allocated to each of the subfields SF1 through SF8 depends on a display discharge time corresponding to a gray scale. For example, in the case of displaying 256 gray scales with 8-bit image data in units of frames, if a unit frame (usually, 1/60 second) is composed of 256 unit times, the first subfield SF1 driven according to image data of the least significant bit has 1 (20) unit time, the second subfield SF2 has 2 (21) unit times, the third subfield SF3 has 4 (22) unit times, the fourth subfield SF4 has 8 (23) unit times, the fifth subfield SF5 has 16 (24) unit times, the sixth subfield SF6 has 32 (25) unit times, the seventh subfield SF7 has 64 (26) unit times, and the eighth subfield SF8 driven according to image data of the most significant bit has 128 (27) unit times. Since the sum of unit times allocated to the subfields SF1 through SF8 is 255, 255 gray scale display can be accomplished. If a gray scale at which there is no display discharge in any subfield is included, 256 gray scale display can be accomplished.
FIG. 5 shows a typical driving apparatus for the PDP 1 shown in FIG. 1. Referring to FIG. 5, the typical driving apparatus for the PDP 1 includes an image processor 66, a logic controller 62, an address driver 63, an X-driver 64, and a Y-driver 65. The image processor 66 converts an external analog image signal into a digital signal to generate an internal image signal composed of, for example, 8-bit red (R) image data, 8-bit green (G) image data, 8-bit blue (B) image data, a clock signal, a horizontal synchronizing signal, and a vertical synchronizing signal. The logic controller 62 generates drive control signals SA, SY, and SX in response to the internal image signal from the image processor 66. The address driver 63 processes the address signal SA among the drive control signals SA, SY, and SX output from the logic controller 62 to generate a display data signal and applies the display data signal to address electrode lines. The X-driver 64 processes the X-drive control signal SX among the drive control signals SA, SY, and SX output from the logic controller 62 and applies the result of processing to X-electrode lines. The Y-driver 65 processes the Y-drive control signal SY among the drive control signals SA, SY, and SX output from the logic controller 62 and applies the result of processing to Y-electrode lines.
FIG. 6 shows driving signals applied to electrode lines according to a conventional address-while-display driving method. In FIG. 6, a reference character SX1 denotes a driving signal applied to an X-electrode line of an XY-electrode line pair performing initial resetting and addressing in a unit frame FR1, and a reference character SY1 denotes a driving signal applied to the Y-electrode line of the XY-electrode line pair performing the initial resetting and addressing in the unit frame FR1. A reference character SX2 denotes a driving signal applied to an X-electrode line of an XY-electrode line pair performing second resetting and addressing in the unit frame FR1, and a reference character SY2 denotes a driving signal applied to the Y-electrode line of the XY-electrode line pair performing the second resetting and addressing in the unit frame FR1. A reference character SXn denotes a driving signal applied to an X-electrode line of an XY-electrode line pair performing last resetting and addressing in the unit frame FR1, and a reference character SYn denotes a driving signal applied to the Y-electrode line of the XY-electrode line pair performing the last resetting and addressing in the unit frame FR1. A reference character SA1 . . . m denotes a display data signal applied from the address driver 63 of FIG. 5 to all address electrode lines.
The conventional address-while-display driving method will be described in detail with reference to FIG. 6.
As shown in FIG. 6, in an address-while-display driving method for a PDP, resetting and addressing are performed on the XY-electrode line pairs X1Y1, X2Y2, . . . , XnYn while a positive voltage Vsh of a third level and a negative voltage Vs1 of a first level are alternately applied to all of the X- and Y-electrode lines X1 through Xn and Y1 through Yn shown in FIG. 1
A resetting process includes a line discharge step ta–t1, an erasure step tb–tc, and iteration steps. Since a second subfield corresponding to a first XY-electrode line pair starts after a first subfield corresponding to the first XY-electrode line pair performing initial resetting and addressing in a unit frame FR1, during a first pulse width period t0–t1, the negative voltage Vs1 of the first level is applied to all of the X-electrode lines X1 through Xn, and simultaneously, the positive voltage Vsh of the third level is applied to all of the Y-electrode lines Y1 through Yn. In the line discharge step ta–t1, during the first pulse width period t0–t1, a negative voltage Vsc of a second level higher than the first level is applied to the X-electrode line X1 of the first XY-electrode line pair X1Y1, and simultaneously, a positive voltage Vre of a sixth level higher than the third level is applied to the Y-electrode line Y1 of the first XY-electrode line pair X1Y1. Accordingly, discharges are provoked in all display cells corresponding to the first XY-electrode line pair X1Y1, thereby uniformly forming wall charges and satisfactorily forming space charges.
During a second pulse width period t1–t2, immediately after the first pulse width period t0–t1 during which the line discharge step ta–t1 is performed, the positive voltage Vsh of the third level is applied to all of the X-electrode lines X1 through Xn, and simultaneously, the negative voltage Vs1 of the first level is applied to all of the Y-electrode lines Y1 through Yn, so that wall charges are uniformly formed and space charges are satisfactorily formed in all of the display cells corresponding to the first XY-electrode line pair X1Y1.
In an erasure step performed for a predetermined time tb–tc, during a third pulse width period t2–t3 immediately after the second pulse width period t1–t2, a positive voltage Veh of a seventh level lower than the third level is applied to the X-electrode line X1 of the first XY-electrode line pair X1Y1, and simultaneously, a negative voltage Vel of an eighth level lower than the first level is applied to the Y-electrode line Y1 of the first XY-electrode line pair X1Y1. Accordingly, wall charges are erased from all of the display cells corresponding to the first XY-electrode line pair X1Y1. However, the space charges satisfactorily remain in the display cells.
The steps of forming and erasing wall charges are sequentially performed on each of the remaining XY-electrode line pairs (see driving signals SX2 and SY2 of FIG. 6).
In FIG. 6, durations td–te, th–ti, and ty–tz are addressing times, during which wall charges are formed in selected display cells, after resetting. These addressing times td–te, th–ti, and ty–tz correspond to times t3–t4, t5–t6, and t2n+1–t2n+2, respectively, during which the negative voltage Vs1 of the first level is applied to all of the Y electrode lines Y1 through Yn. During these addressing times td–te, th–ti, and ty–tz, the negative scan voltage Vsc of the second level higher than the first level is applied to the respective Y-electrode lines of XY-electrode line pairs X1Y1, X2Y2, and XnYn to be addressed, and simultaneously, positive display data signals are applied to all of the address electrode lines A1 through Am shown in FIG. 1. Accordingly, opposite discharges occur among the Y-electrode line of an XY-electrode line pair to be addressed and selected address electrode lines, thereby forming positive wall charges around the Y-electrode of selected display cells. In the selected display cells, display discharges are performed in response to pulses due to a wall voltage induced from the wall charges.
According to the conventional address-while-display driving method, display voltages that are alternately applied to the X- and Y-electrode lines of each of all XY-electrode line pairs are constant. Accordingly, a voltage that is applied to each XY-electrode line pair is relatively higher during the addressing times td–te, th–ti, and ty–tz than during other times, and thus a maximum of the address voltage Va applied to selected lines among all address electrode lines A1 through Am decreases. In other words, an applicable range, i.e., margin, of the address voltage Va is narrowed. When the margin of the address voltage Va is narrowed, display performance may be degraded due to incorrect and inaccurate addressing.